1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the invention relates to a semiconductor memory chip capable of easily analyzing an internal operation thereof.
2. Description of the Related Art
Conventionally, a probing method and a method using an electron beam have been used to analyze an internal operation of a semiconductor chip.
The probing method is to directly read timing of internal signals and variations in voltage by applying a probe to a node in a semiconductor chip. In this method, the probe needs to be directly applied to the node. Therefore, a sample chip for evaluating an internal operation of the chip has to be formed through a process such as a removal of an oxide film from above a wiring layer. This method requires a lot of time to evaluate the internal operation. Since, moreover, the probe is brought into direct contact with the node in the chip, the sample chip is easily destroyed at the time of the evaluation. In this case, a sample chip is often formed from the beginning; thus, it is difficult to evaluate the internal operation of the chip with efficiency.
The method using an electron beam is to evaluate timing of internal signals and variations in voltage by emitting an electron beam to a node in a semiconductor chip and two-dimensionally reading variations in the potential of the node. This method necessitates a very expensive, large-sized apparatus and a sample chip for the evaluations. This method therefore requires a lot of time to make the evaluations and increase the costs therefor. As in the above probing method, it is difficult to make the evaluations with efficiency.
Since the above conventional methods require a sample chip and a lot of time, efficient evaluations cannot be performed for a target chip. The methods also require a special-purpose apparatus and thus efficient evaluations are difficult to make in terms of costs. Moreover, the conventional methods are not suitable for acquiring a large amount of data in order to make evaluations in view of variations in lots and wafers.
As a method of resolving the above problems, a semiconductor memory device that is easy to verify and evaluate its characteristics has recently been proposed (disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 2001-52498 corresponding to U.S. Pat. No. 6,252,820). According to the proposed semiconductor memory device, an SRAM (static random access memory) for reading/writing data to/from a memory cell array by generating an internal control signal from a control signal generation circuit in response to a clock signal includes a monitor control signal input terminal, an output buffer for monitoring, and a monitor output terminal. Such a configuration allows the timing and pulse widths of internal control signals that are generated in response to clock signals to be monitored.
In the semiconductor memory device, however, some of the internal control signals are output from the special-purpose monitor output terminal. The monitor output terminal is covered with an envelope when the SRAM is packaged. Thus, the characteristics of the device cannot be verified or evaluated after the packaging of the SRAM.
As described above, the prior art semiconductor memory device can monitor the timing and pulse widths of internal control signals. However, the device has a problem that its characteristics cannot be verified or evaluated after packaging.
A semiconductor memory device according to an embodiment of the present invention comprises a memory cell array, a plurality of input/output terminals to input cell data written to the memory cell array and output cell data read from the memory cell array, a test mode setting circuit which sets a test mode to monitor a plurality of timing signals which control input/output operation timing of the cell data, and switch circuits which simultaneously output the plurality of timing signals from the plurality of input/output terminals in the test mode.